Design and Implementation of High Performance Dynamic Memory Controller

Download Now
Provided by: Research In Motion
Topic: Storage
Format: PDF
This controller is targeted at high bandwidth applications such as live video processing. It is designed to drive 256-bit DDR SDRAM memory. The DDR SDRAM architecture employs a 2n-prefetch architecture, where the internal data bus is twice the width of the external data bus. A single read or write cycle involves a single 2n-bit wide, one-clock-cycle data transfer at the core, and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O. Thus, this enables high-speed operation as the internal column accesses are half the frequency of the external data transfer rate.
Download Now

Find By Topic