International Journal of Latest Trends in Engineering and Technology (IJLTET)
The multiplication operation is present in many parts of a digital system or digital computer, most notably in signal processing, graphics and scientific computation. With advances in technology, various techniques have been proposed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speeds, low power compact VLSI implementations. These three parameters i.e. power, area and speed are always traded off. In this paper, high-performance two's compliment square multiplier (number of bits in multiplier and multiplicand are equal) algorithm is presented to reduce the total number of Partial Product (PP) rows generated, almost by half to achieve fast multiplication.