Design and Implementation of Hybrid CMOS-SET Half Adder and Full Adder Circuits
Single Electron Transistors (SETs) have high integration density and ultra-low power consumption, which makes them promising candidates as basic circuit elements of the future generation ULSI circuits. However, Single electron transistors have extremely poor driving capabilities so that direct application to practical circuits is as yet almost impossible. A technique to overcome this problem is to build hybrid circuits of SETs and CMOS. In this paper, hybrid SET-CMOS half adder and full adder are designed and implemented. The MIB compact model for SET device and BSIM4.6.1 model for CMOS are used. All the circuits are verified by means of T-Spice simulation software.