Provided by: International Journal of Latest Trends in Engineering and Technology (IJLTET)
In this paper, the authors describe about 16 bit ALU using clock gating. This clock gating generally reduces the consumed amount of power when compared to normal implementation. Clock power reduces 60% of total dynamic power. Theoretically, they can reduce at a maximum of 93.7% of dynamic power. This clock gating internally contains 2 types that are latch based and latch free clock gating in which 88.23% can be reduced using latch based and 70.5% can be reduced using latch free clock gating.