Design and Implementation of Low Power 16 Bit ALU with Clock Gating
The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence, the power consumption of the ALU is a major concern. In this paper, a low power 16-bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique and the results are compared with conventional ALU design. A carry skip adder with variable block length is used for the arithmetic unit to achieve better performance. The design is then implemented in Xilinx Spartan 3E FPGA. The ALU achieves a maximum frequency of 65.19MHz with a dynamic power dissipation of 1.98mW when operated at 15MHz.