Design and Implementation of Low Power Multiplier Using Vedic Multiplication Technique

Provided by: Serials Publications
Topic: Hardware
Format: PDF
In this paper, a low power multiplier is presented. The multiplier implemented here is based on the ancient Vedic multiplication technique. The Urdhva-tiryakbhyam and Nikhilam sutras are used for multiplication. The multiplier based on ancient technique is compared with the modern multiplier to highlight the power and speed advantages in the Vedic multipliers. The Vedic multiplier is tested by using BIST (Built-In Self-Test) and it is found Fault free. The results are compared with the Booth's multiplier in terms of time delay and power. The high speed processor requires high speed and low power multipliers and the Vedic multiplication technique are very much suitable for this purpose.

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