Design and Implementation of Low Power Pipelined Coefficient Ordered FFT Processors Using Body Bias Technique
In this paper, the authors present a modified coefficient ordering based pipelined 16 point FFT processor. The fixed radix- 4 and single path pipelined architecture is used in this FFT design. The pipelined architecture provides higher throughput rate comparing with the ordinary pipelined architecture. The low power issue is addressed by minimizing the switching activity using minimum Hamming distance transition. The switching activity of twiddle computation is thus reduced from 192 to 78, i.e. 59% reduction. The multiplier less architecture uses reduced number of multipliers to realize complex multiplication.