The multiplier and Multiplier-ACcumulator (MAC) are the essential elements of the digital signal processing such as filtering, convolution, and Inner products. In this paper, a new architecture of MAC for high-speed arithmetic has been designed. By combining multiplication with accumulation and devising a hybrid type of Carry Save Adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The designed CSA uses 1's-complement based Modified Booth's Algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands.