Design and Implementation of Pipelined 32-Bit Advanced RISC Processor for Various D.S.P Applications

Provided by: International Journal of Computer Science and Information Technologies Topic: Data Centers Date Added: Jan 2012 Format: PDF
In this paper, the authors propose 32-bit pipelined RISC processor using VLIW architectures. This processor is especially used for both D.S.P applications and general purpose applications. Reduced instruction is the main criteria used to develop in this processor. With a single instruction scheme, more executions can be done using S.I.M.E. processor consists of the blocks namely program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incrementer circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core.

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