Design and Implementation of Power Efficient Micro Pipelined GALS Based 2-D FFT Processor Core
Today's complex SOC solutions demand low power processors. Synchronous processors which consume more than 40% of power in clock circuitry are being conveniently replaced by low power Delay-Insensitive (DI) asynchronous logic. In this paper, a micro-pipelined GALS based 2D Fast Fourier Transform (FFT) processor is designed and implemented to perform power, area and timing analysis. The implemented design has given power advantage of 78.22% and timing advantage of 39.99% when compared with similar synchronous 2D FFT processor.