Design and Implementation of Q-algorithm for Data Collision Reduction in EPC GEN-2 based on FPGA
EPC is the new Electronic Product Code that replaces the older UPC (Universal Product Code) found on many item labels. EPC Gen-2 is the new version standard than EPC Gen-1. EPC Gen-2 is an Electronic Product Code which is globally accepted standard in RFID. The data collision in RFID tags is reduced using anti-collision Q-algorithm. In this paper, design and implementation of Q-algorithm is described to solve data collision in RFID tags using Verilog HDL. The whole design will be developed using Xilinx ISE 12.2 and will be simulated using Modelsim 6.3c and will be implemented on Virtex 4 FPGA.