Design and Implementation of Real-Time Transactional Memory

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Provided by: Vienna University of Economics and Business
Topic: Hardware
Format: PDF
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is also appealing for real-time systems. In this paper an implementation of Real-Time Transactional Memory (RTTM) in the paper of a real-time java Chip Multi-Processor (CMP) is presented. To provide a predictable and analyzable solution of transactional memory, the transaction buffer is organized fully associative. Evaluation in an FPGA shows that an associativity of up to 64-way is possible without degrading the overall system performance.
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