Design and Implementation of Truncated Multiplier in FIR Filter

Provided by: Applications of Engineering Technology and Science (AETS)
Topic: Hardware
Format: PDF
Low-cost Finite Impulse Response (FIR) designs are presented using the concept of faithfully rounded truncated multiplier. This multiplier design is usually considered where the maximum absolute error is no more than 1 unit of least position. And also this truncated multipliers offer significant improvement in area, delay and power. The proposed method jointly consider the deletion, reduction, truncation and rounding of partial product bits in order to minimize the number of full adders and half adders during tree reduction. In addition, the truncated multiplier design also has smaller delay due to the smaller bit width in the final carry-propagate adder.

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