Design and Implementation of TSPC and E-TSPC Based Low Power Single Phase Clock Distribution in SOC Technology

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Provided by: The International Journal of Advanced Research Foundation (IJARF)
Topic: Hardware
Format: PDF
The clock distribution network synchronizes the flow of data signal between data path. One of the important functional blocks in frequency synthesizer is the high speed dual module pre-scaler. Normally for a multi-clock domain network, the authors develop a multiple PLL to cater the need, this paper aim for developing will supply for the multi clock domain network. A Voltage Controlled Differential Injection Locked Frequency Divider (VCDILFD) is used as the first frequency divider in the PLL feedback to reduce power consumption and eliminate the need for an off-chip frequency divider.
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