International Journal of Engineering Trends and Technology
A new Very Large Scale Integration (VLSI) algorithm for a Discrete Hartley Transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The concurrent execution of the DHT algorithm can be achieved by splitting on several parallel parts efficiently. In addition, the hardware complexity can be significantly reduced using sub-expression sharing technique of the proposed algorithm in highly parallel VLSI implementation. With efficient sharing of multipliers having the same constant and using the advantages of the proposed algorithm, the numbers of multipliers and adders used has been significantly reduced and is kept at a minimum compared with that of the existing algorithms.