International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE)
In this paper, the authors present an area efficient implementation of a high performance parallel multiplier. Radix-4 Booth multiplier with 3:2 compressors and radix-8 Booth multiplier with 4:2 compressors are presented here. The design is structured for mxn multiplication where m and n can reach up to 126-bits. Carry look-ahead adder is used as the final adder to enhance the speed of operation. Finally, the performance improvement of the proposed multipliers is validated by implementing a higher order FIR filter.