Design and Optimization Approaches in Double Gate Device Architecture

Provided by: Engg Journals Publications
Topic: Hardware
Format: PDF
According to Moore's law, the number of transistor embedded on Integrated Circuit (IC) doubles approximately every two years. Thus, the size of Metal-Oxide Semi-conductor Field Effect Transistor (MOSFET) has to be scaled down as an increase in packing density. In current technology, the size of a transistor has shrunk below 45nm and it has already reached its physical limit. Any attempt to shrink the MOSFET beyond this limit will expose MOSFET device to various Short Channel Effects (SCEs) problems.

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