Journal of Computers (JCP)
For System-on-Chip (SoC) test based on IP cores integration reuse, the IEEE 1500 standard has given specific testing architecture. In this paper, the authors aim at building controllable test architecture for IP cores on SoC based on IEEE 1500 Standard. The technique applied is referred to as test control switch which is configured to the wrapper of IP cores. They design a Switch Control Register (SCR) to configure the state of the switches, and apply the expanded TAP (eTAP) based on IEEE 1149.1 standard to control the SCR and the wrapper of IP cores.