Design and Performance Analysis of Fault Secure Network-on-Chip Using FPGA

Provided by: International Journal of Advanced Research in Computer Engineering & Technology
Topic: Networking
Format: PDF
Network on-chip is a novel designing communication protocol. It creates a communication between the on-chip cores. It has been proposed as one of the interconnect solutions for future Systems-on-Chip (SoCs). This paper presents an offline/online concurrent scan based Built-In-Self-Test (scan-BIST) method for a Network-on-Chip (NoC). The proposed architecture contains a special scan cell and an Embedded Test Core (ETC) as its test source. The ETC performs a static flow control and a centric average power consumption control during the proposed test mechanism. This shows the design and implementation of a novel pipeline circuit-switched switch to support guaranteed throughput.

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