Memories are integral parts of most of the digital devices and hence reducing power consumption of memory is very important in improving the system performance, efficiency and stability. The requirement in present scenario is low power devices. Since these are critical component in high performance processors. Keeping this point in view, this paper proposes on 6T CMOS SRAM. The proposed and conventional 16-bit SRAM has been designed and simulated for 180nm, 100nm and 90nm CMOS technologies.