Design and Performance Comparison of Average 8T SRAM with Existing 8T SRAM Cells

Provided by: Auricle Technologies
Topic: Hardware
Format: PDF
In this paper, the authors present 8T SRAM cell by using various techniques. The conflicting design requirement of read versus write operation in a conventional 8T SRAM bit cell is eliminated using separate read/write access transistors. Read stability and the write-ability can be optimized independently by optimizing the respective access transistor size. A new average-8T write/read decoupled SRAM architecture for low-power sub/near-threshold SRAM used in power-constraint applications such as biomedical implants and autonomous sensor nodes.

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