Design and Performance Evaluation of a Reconfigurable Delta MIN for MPSOC

Provided by: INRIA
Topic: Hardware
Format: PDF
Multi-Processor System-on-Chip (MPSoC) is a concept that aims at integrating multiple hardware and software in a chip. Multistage interconnection network has been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry for solving the problems related to an on-chip communication. This paper presents the design of reconfigurable Delta MINs in which the connections change dynamically at run time. Using SystemC timed simulations, performance evaluation of a Delta MINs are given and analyzed.

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