International Journal of Computer Applications
In recent days, advanced digital process demands more sophisticated parameters such as throughput, power and area. It is very difficult to maintain high throughput while maintaining optimum power consumption and cell area. In most of the digital systems, multipliers are deciding their performance in terms of above parameters. In the present paper, high speed Vedic multipliers are designed with pipeline technology. As the MAC speed is decided by Vedic multiplier, in the present paper Multiplier-and-ACcumulator (MAC) is designed with two way pipeline technology to meet high throughput.