Design and Realisation of Low Leakage 1-Bit CMOS Based Full Adder Cells for Mobile Applications
For the most recent CMOS feature sizes (e.g., 180nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. As technology scales into the nano meter regime leakage power and noise immunity are becoming important metric of comparable importance to active power, delay and area for the analysis and design of complex arithmetic and logic circuits. In this paper, low leakage 1-bit full adder cells are proposed for mobile applications. Noise immunity has been carefully considered since the significant threshold current of the low threshold voltage transition becomes more susceptible to noise.