In this paper, the authors proposed the methodology for double precision floating point division using radix-8. This is the improved method of producing high speed. The architecture is based on look-up table and comparator. Double precision floating point division offer qualities like high speed on the expense of larger area and circuit complexity. Also floating point value can be represented by using IEEE-754 standard for division. This design will be simulated in Xilinx and it can be highly portable if it is design on a Field Programmable Gate Array (FPGA).