Design and Simulation of Energy-Efficient 8-Bit Input Buffer for NoC Router

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Provided by: International Journal of Recent Technology and Engineering (IJRTE)
Topic: Hardware
Format: PDF
In NoC (Network on Chip), the power consumption is major issue while designing. In NoC router, conventional input buffer consume more energy. The paper is focused on the energy-efficient design of 8-bit input buffers, which use the characteristic of transmission of data on NoC that has probability of transmitting a zero signal is more than that of transmitting a signal one. The design of energy efficient 8-bit input buffer reduces the power consumption by 48% and the chip area 29% with calculating the gates count as compared with conventional 8-bit input buffer by using 65 nm CMOS technology in simulation.
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