National Institute of Technology, Tiruchirappalli
In the downlink module of Orthogonal Frequency Division Multiple Access (OFDMA) system, there is needed an alterable points FFT processor. Therefore, it is meaningful to design a FFT processor for the FFT processor which input data points could be alterable. In this paper the variable input FFT processor is designed to meet the requirements of OFDMA system. For this, in this paper, the authors select the 2D Fourier transform algorithm as the kernel algorithm, use VHDL language to present in detail a design of two-stage pipeline structure, use QuartusII and ModelSim SE for the simulation, and verify on the EP3C25Q240CSN chip FPGA.