Design and Simulation of Practical NOC 2x2 Torus Topology
The fundamental unit of building a network-on-chip is the router; it directs the packets according to a routing algorithm to the desired host. In this paper, a router is designed using Verilog language and implemented on Spartan-3E FPGA (Field-Programmable Gate Array) with the help of Integrated Software Environment (ISE 10.1). The utilization of the Spartan 3E resources is excellent (for example the number of slices required doesn't exceed 3%). After that, a (2×2) mesh topology and a (2x2) torus topology network are designed and implemented using FPGA.