Design and Synthesis of Reversible Fault Tolerant Carry Skip Adder/Subtractor
According to the researchers, the traditional irreversible logic circuits i.e. made up by using conventional logic gates such as AND, OR, EX-OR, etc. Reversible logic will be having more demand in future computation technology because of its zero power dissipation under ideal conditions. This paper proposes the fault tolerant carry skip adder/subtractor by using parity preserving reversible logic gates. According to the control logic input the proposed design can works as a carry skip adder or carry skip subtractor.