International Journal of Latest Trends in Engineering and Technology (IJLTET)
In this paper, the operation of Wallace Tree Multiplier (WTM) is performed by recoding the multiplier bits with booth logic. In modified booth, the authors can multiply two 2's complement numbers without sign bit extension. Recoding the multiplier with increasing of radix is one of the best ways to increase the speed of the booth multiplication algorithm. In this architecture, they are using radix-8 modified booth algorithm to generate partial products. To sum partial products concurrently compression techniques can be used. The proposed Wallace Tree Multiplier (WTM) is implemented with Verilog HDL coding and synthesis is done by Cadence RTL compiler in 0.18 um technology.