Design and Verification of Low Power SRAM Using 8T SRAM Cell Approach
SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. Advances in chip designing have made possible the design of chips at high integration and fast performance. Lowering power consumption and increasing noise margin have become two central topics in every state of SRAM designs. The conventional 6T SRAM cell is very much prone to noise during read operation. To overcome the read SNM problem in 6T SRAM cell, researchers have considered different configurations for SRAM cells such as 8T, 9T, 10T, etc. bit-cell design.