Design and Verification of USB 3.0 Link Layer (LTSSM)
USB is an industry standard developed in the mid-1990s, it defines the cables, connectors and protocols used in a bus for connection and communication between computers and electronic devices. In this proposed design it mainly includes USB 3.0, LTSSM. The Link Training and Status State Machine (LTSSM) have downstream and upstream ports. Transitions of all 12 link states and their subs -states of both downstream and upstream have been designed. The proposed model is implemented using Verilog HDL. Proposed model in this paper has been verified using SystemVerilog.