Research In Motion
The scaling of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been governed over past several decades and is now becoming very critical due to its scaling limit and its short channel effects (SCE). In this paper, several design consideration and the effects of various process parameters variation on the device performance is carried out for sub-40nm engineered MOSFET. Virtual fabrication of sub-40nm bulk MOSFET is carried out under channel engineering and source drain engineering process. These structures enable more aggressive device scaling in nano-scale region because of their ability to control short channel effects.