Design Enhancements for In-Cache Computations

Provided by: University of Northern Iowa
Topic: Hardware
Format: PDF
New programming models and increased off-chip bandwidth demands of multicore processors have changed the nature of the memory wall problem, and innovative hardware and software solutions are emerging to combat the resulting latency and power issues. Emerging processor designs include organizations of on-chip resources that diverge from the classical multicore model. One example of such a system increases core counts along a new design dimension by embedding simple cores into the cache hierarchy of more complex, conventional cores.

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