Design, Implementation and Analysis of 10bit, 80MS/s Pipeline ADC Using OPAMP Sharing Technique in Cadence Tool
In this paper, A 10 bit, 80 MS/s pipeline ADC is design using OPAMP sharing technique. The OPAMP is shared between all the consecutive pipeline stages, so that power consumption and die area can minimize. The A/D is designed, implemented and analyzed in standard gpdk 180 nm technology library using cadence tool. This converter achieves 68 dB spurious free dynamic range, 59 dB signal-to-noise-plus-distortion ratio,9.58 effective number of bits for a 90 MHz input at full sampling rate, and consumes 30mW from a 1.8 V supply.