Design, Implementation and Analysis of Digital Phase Locked Loop Using Charge Pump in 45nm CMOS Technology

Provided by: Research and Educational Society
Topic: Hardware
Format: PDF
Phase Locked Loops (PLLs) are widely used in high speed data communication systems. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a mixed signal PLL which must operate in the GHz range with low jitter, low phase noise and less lock time. The proposed architecture of digital PLL has been implemented using BPTM 45nm CMOS Technology in LT spice tool.

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