Design & Implementation of PCI Express BUS Physical Layer Using VHDL

In this paper, the authors present the proposal of the implementation of the physical link layer of PCI-Express, as is defined in PCI Express1.0. The architecture presented here contains the transmission and receiver modules which ensure the reliably conveying of the Transaction Layer Packet (TLP) and Data Link Layer Packet (DLLP) between two components using the PCI-Express protocol. This paper explains how the implementation makes the reliably conveying, through the addition of a start and end bits to each data coming in from the transaction and data link layer in the transmit side, and how the packets are processed in receiver side.

Provided by: Auricle Technologies Topic: Hardware Date Added: Jul 2014 Format: PDF

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