Design Low Power Full-Adders for Arithmetic Applications

Provided by: International Journal of Emerging Science and Engineering (IJESE)
Topic: Hardware
Format: PDF
In this paper, the authors present low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and COUT.

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