Design Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme

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Provided by: IRD India
Topic: Hardware
Format: PDF
In this paper, analysis of average power, delay and power delay product is done by shift register using 90 nm technology. Low power flip-flops are crucial for the design of low-power digital systems. As Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are scaled down to nanometer ranges, Complementary MOS (CMOS) circuits total Power consumption has a new definition. Due to integration of millions of components and shrinking process technology, now-a-days leakage power tends to play a major role in total power consumption.
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