Provided by: International Journal of Engineering Research and Development (IJERD)
Date Added: Oct 2013
In this paper, the authors develop a methodology for designing lower-error and area efficient 2's complements fixed width multiplier. In these multipliers, basic multiplications follow the Baugh-Wooley algorithms and have been implemented using Field Programmable Gate Array (FPGA) devices. The approach is based on the fact that the multiplication operations used in multimedia applications (such as DSP) usually have the special fixed width property i.e., their input data and output product have the same bit width.