International Journals of Advanced Information Science and Technology (IJAIST)
An Extended True Single Phase Clock (E-TSPC) based divide-by-2/3 counter design for low supply voltage and low power consumption applications are presented. By using a wired OR scheme; only one transistor is needed to implement both the counting logic and the mode selection control. This can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC Flip-Flops (FFs). Since, the number of transistor stacking between the power rails is kept at merely two; the proposed design is sustainable to low operations (531MHz at 0.6V) for the power saving purpose.