Design of 8-Port Adaptive Network on Chip

Provided by: International Journal of Innovative Research in Science, Engineering and Technology (IJIRSET)
Topic: Hardware
Format: PDF
Networks-on-Chip (NoCs) have emerged as a promising on-chip inter-connects for future multi/many-core architectures as NoCs are able to scale communication links with the growing number of cores. In this paper, the authors present an adaptive route allocation algorithm which provides a required level of QoS (guaranteed bandwidth) coupled with an adaptive buffer assignment scheme which reassigns buffer blocks up-demand. In addition, the adaptivity requires a comprehensive, hardly invasive, runtime discernibility infrastructure, i.e., using supervising components, in order to collect data on the system put forward.

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