Design of a 6-Bit 500MS/s CMOS A/D Converter with Comparator-Based Input Voltage Range Detection Circuit

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Provided by: Journal of Semiconductor Technology and Science (JSTS)
Topic: Hardware
Format: PDF
A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this paper, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector.
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