Design of a High Speed FPGA-Based Classifier for Efficient Packet Classification

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Provided by: IJCTT-International Journal of Computer Trends and Technology
Topic: Hardware
Format: PDF
Packet classification is a vital and complicated task as the processing of packets should be done at a specified line speed. In order to classify a packet as belonging to a particular flow or set of flows, network nodes must perform a search over a set of filters using multiple fields of the packet as the search key. Hence the matching of packets should be much faster and simpler for quick processing and classification. A hardware accelerator or a classifier has been proposed here using a modified version of the HyperCuts packet classification algorithm.
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