Design of a Low Drop-Out Voltage Regulator using VLSI

Provided by: International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE)
Topic: Hardware
Format: PDF
A low-voltage Low-DropOut (LDO) voltage regulator that can operate with a very small input - output differential voltage with nm CMOS technology in turn increasing the packing density, provides for the new approaches towards power management is proposed. A simple symmetric operational trans-conductance amplifier is used as the Error Amplifier (EA), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the LDO regulator. In the rail-to-rail output stage of the EA, a power noise cancellation mechanism is formed, minimizing the size of the power MOS transistor.

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