Provided by: International Journal of Engineering Trends and Technology
Date Added: Jan 2014
In this paper, the authors describe a CMOS analogy voltage supper buffer designed to have extremely low static current consumption as well as high current drive capability. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation. The name of applied technique is transistor gating technique, which gives the high speed buffer with the reduced low power dissipation (1.105%), low leakage and reduced area (3.08%) also.