Provided by: International Journal of Computer Theory and Engineering (IJCTE)
Date Added: Jan 2014
A Non-Overlapping Clock (NOC) generator circuit is designed for the successful operation of High Voltage Generator (HVG) implementation in low-power applications like Radio Frequency IDentification (RFID) tag EEPROM. The NOC generator has been implemented in 0.18 CMOS process. The designed NOC can generate two stable anti-phase clock signals as output, which is used in Charge Pump (CP) circuit with low power dissipation. The NOC generator required lower power dissipation with 359.87 nW under power supply Voltage Drain Drain (VDD) 1.8 V.