Design of a Parallel Pipelined FFT Architecture with Reduced Number of Delays

Provided by: International Journal of Latest Trends in Engineering and Technology (IJLTET)
Topic: Hardware
Format: PDF
In this paper, the authors present a novel approach to design a four and eight parallel pipelined Fast Fourier Transform (FFT) architecture based on canonic signed digit multiplier. This approach is based on use of decimation in time algorithm which reduces the number of delay elements up to some extent compared to decimation in frequency based design. The number of delay elements required for N point FFT architecture is N-4 which is comparable to that of delay feedback schemes. The number of complex adders required is approximately 50% less than the other feedback designs.

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