International Journal for Technological Research in Engineering (IJTRE)
A low-complexity LUT-Log-BCJR architecture, achieves a low area and hence a low power consumption by decomposing the LUT-Log-BCJR algorithm into its most fundamental ACS operations. This ACS based architecture may be readily reconfigured for different turbo codes or decoding algorithms and validated the architecture by implementing an LTE turbo decoder. A turbo decoder is typically one of the most computation-intensive parts in a 4G wireless receiver. Increased complexity and performance requirements and the need to reduce power and area are significant challenges for turbo decoder hardware implementation.