Design of an Energy-Efficient 32-Bit Adder Operating at Subthreshold Voltages in 45-nm CMOS
Low-power circuits have been quickly increasing their importance due to the high cost in design of cooling systems with complex chip packaging techniques, and also due to the low energy consumption requirement of portable devices powered by a limited battery capacity. In this paper, the authors present the design of a low-power 32-bit adder that is a basic functional unit in most computational platforms. Its energy efficiency is highly achieved while operating in the subthreshold regime. Simulation results in 45-nm PTM CMOS show the adder consumes only 22 fJ per computation at 0.2 V with maximum operating frequency of 3.8MHz.